The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise, qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIG. 1, a hard disk drive (HDD) 10 includes a hard disk assembly (HDA) 12 and a HDD printed circuit board (PCB) 14. The HDA 12 includes one or more circular platters 16, which have magnetic surfaces that are used to store data magnetically. Data is stored in binary form as a magnetic field of either positive or negative polarity. The platters 16 are arranged in a stack, and the stack is rotated by a spindle motor 18. At least one read/write head (hereinafter, “head”) 20 reads data from and writes data on the magnetic surfaces of the platters 16.
Each head 20 includes a write element, such as an inductor, that generates a magnetic field and a read element, such as a magneto-resistive (MR) element, that senses the magnetic field on the platter 16. The head 20 is mounted at a distal end of an actuator arm 22. An actuator, such as a voice coil motor (VCM) 24, moves the actuator arm 22 relative to the platters 16.
The HDA 12 includes a preamplifier device 26 that amplifies signals received from and sent to the head 20. When writing data, the preamplifier device 26 generates a write current that flows through the write element of the head 20. The write current is switched to produce a positive or negative magnetic field on the magnetic surfaces of the platters 16. When reading data, the magnetic fields stored on the magnetic surfaces of the platters 16 induce low-level analog signals in the read element of the head 20. The preamplifier device 26 amplifies the low-level analog signals and outputs amplified analog signals to a read/write (RAN) channel module 28.
The HDD PCB 14 includes the R/W channel module 28, a hard disk controller (HDC) module 30, a processor 32, a spindle/VCM driver module 34, volatile memory 36, nonvolatile memory 38, and an input/output (I/O) interface 40. During write operations, the R/W channel module 28 may encode the data to increase reliability, such as by using error correction coding (ECC), run length limited (RLL) coding, Reed-Solomon encoding, etc. The R/W channel module 28 then transmits the encoded data to the preamplifier device 26.
During read operations, the R/W channel module 28 receives analog signals from the preamplifier device 26. The R/W channel module 28 converts the analog signals into digital signals, which are decoded to recover the original data. The HDC module 30 controls operation of the HDD 10. For example, the HDC module 30 generates commands that control the speed of the spindle motor 18 and the movement of the actuator arm 22. The spindle/VCM driver module 34 implements the commands and generates control signals that control the speed of the spindle motor 18 and the positioning of the actuator arm 22.
Volatile memory 36 and nonvolatile memory 38 may be used to store information such as controller data, cached data waiting to be written to the HDA 12 or read by the I/O interface 40, and/or temporary values. Volatile memory 36 may include Dynamic Random Access Memory (DRAM), Synchronous DRAM, Rambus DRAM, etc. Nonvolatile memory 38 may include flash memory (including NAND and NOR flash memory), static RAM, magnetic RAM, and multi-state memory, in which each memory cell has more than two states.
Using nonvolatile memory 38 to cache data waiting to be written to the HDA 12 or read by the I/O interface 40 has a number of possible benefits. These benefits include faster access time, higher transfer rate, power savings, quicker resumption from a hibernate state, and greater reliability. Data read from the HDA 12 or not yet written to the HDA 12 can be accessed more quickly from nonvolatile memory 38 than from the HDA 12.
Further, data can be accessed from nonvolatile memory 38 without having to power the HDA 12 and spin the platters 16. The HDA 12 may then only require power intermittently to provide read data to nonvolatile memory 38 and flush write data from nonvolatile memory 38. While the platters 16 are not rotating, the HDA 12 is much less prone to physical damage, such as from drops or sudden impacts.
The HDC module 30 communicates with an external device (not shown), such as a host adapter within a host device, via the I/O interface 40. The HDC module 30 may receive data to be stored from the external device, and may transmit retrieved data to the external device. The processor 32 processes data, including encoding, decoding, filtering, and/or formatting.
Additionally, the processor 32 processes servo or positioning information to position the heads 20 over the platters 16 during read/write operations. Servo, which is stored on the platters 16, ensures that data is written to and read from correct locations on the platters 16. In some implementations, a self-servo write (SSW) module 42 may write servo on the platters 16, using the heads 20, prior to storing data in the HDD 10.